1. Field of the Invention
The invention relates generally to through substrate vias within microelectronic substrates. More particularly, the invention relates to enhanced performance through substrate vias within microelectronic substrates.
2. Background of the Invention
Microelectronic structures, and in particular semiconductor structures, include microelectronic devices such as semiconductor devices. The microelectronic devices, such as the semiconductor devices, are located and formed over a microelectronic substrate, such as a semiconductor substrate. The microelectronic devices are connected and interconnected using patterned conductor layers that are separated by dielectric layers.
In addition to the connection and interconnection of microelectronic devices within a microelectronic structure while using patterned conductor layers that are separated by dielectric layers, microelectronic structures, such as but not limited to semiconductor structures, also frequently use through substrate via structures that provide an electrical connection from a top side to a bottom side of a microelectronic substrate, such as a semiconductor substrate.
Through substrate vias when used within microelectronic substrates may serve functions that include, but are not necessarily limited to, microelectronic substrate grounding functions and microelectronic substrate electrical biasing functions.
While through substrate vias within microelectronic substrates serve valuable functions within microelectronic structures, through substrate vias within microelectronic substrates are not entirely without problems. In particular, through substrate vias are often difficult to efficiently fabricate with a comparatively narrow linewidth (i.e., in a range from about 1 to about 3 microns), while completely penetrating through a microelectronic substrate, such as a semiconductor substrate, having an increased thickness.
Various aspects of through substrate vias within microelectronic structures are known in the microelectronic fabrication art.
For example, Sinha (or Sinha et al.), in U.S. Pub. No. 2004/0072422, U.S. Pub. No. 2005/0200027 and U.S. Pub. No. 2005/0247943, teaches various methods for forming a through wafer via through a semiconductor substrate. Each particular method uses in-part a plating method for forming the through wafer via.
In addition, MacNamara et al., in U.S. Pub. No. 2006/0275946, teaches a method for forming a through wafer via within a microelectronic structure. This particular method uses in-part the through wafer via as a location for electrically connecting a discrete electrical device.
Further, Rybnicek, in U.S. Pub. No. 2007/0045820, teaches another method for forming a through wafer via through a semiconductor substrate. This particular method includes plating a conductor material within a blind aperture within a semiconductor substrate, and then planarizing a back surface of the semiconductor substrate to expose the bottom surface of the plated conductor material.
Finally, Savastiouk et al., in U.S. Pat. No. 7,186,586, teaches a packaging substrate that includes a semiconductor interposer that includes through wafer via that includes a contact pad that protrudes from the semiconductor interposer. The protruding contact pad is formed and located to register with an aperture within a semiconductor chip which is intended to mate with the semiconductor interposer and the packaging substrate.
The use of through substrate vias is likely to be of continued prominence and importance as microelectronic device and microelectronic structure dimensions decrease, and as microelectronic circuit functionality and performance requirements increase. To that end, desirable are through substrate via structures having enhanced performance, and methods for fabricating those through substrate via structures.